1. Technical Field
The embodiments described herein generally relate to phase change random access memory apparatuses, and more particularly, to a phase change random access memory apparatus for controlling data transmission.
2. Related Art
A phase change random access memory (hereinafter, referred to as ‘PRAM’) apparatus contains unit cells each of which includes a switching device (e.g., diode) coupled to a word line, and a single element variable resistor (GST; GexSbyTez) coupled to a bit line. Such a PRAM is capable of storing data in the unit cells by reversibly controlling the physical phase of the GST in response to electrical pulses.
Usually, a PRAM apparatus has a hierarchical structure together with other phase change memory apparatuses. For instance, a PRAM apparatus includes a plurality of banks each having a plurality of mats. Each individual mat includes sub blocks arranged as cell array units. With this structure, data can be read out from a selected cell array, or written into a selected cell array from an outside system.
In order to maintain the functional stability of reading or programming operations, it is necessary to preserve read data for a predetermined reading time for a read operation, or to preserve write data for a predetermined programming time for a write operation. Therefore, each sub block including the cell array is required to have latch circuits for temporarily holding data therein. In order to fulfill this requirement, a PRAM apparatus must be enlarged and its integration density increased.